revision 1.1 jan. 2004 1 r0201-STC62WV5128 very low power/voltage cmos sram 512k x 8 bit ? wide vcc operation voltage : 2.4v ~ 5.5v ? very low power consumption : vcc = 3.0v c-grade: 29ma (@55ns) operating current i -grade: 30ma (@55ns) operating current c-grade: 24ma (@70ns) operating current i -grade: 25ma (@70ns) operating current 0.45ua (typ.) cmos standby current vcc = 5.0v c-grade: 68ma (@55ns) operating current i -grade: 70ma (@55ns) operating current c-grade: 58ma (@70ns) operating current i -grade: 60ma (@70ns) operating current 2.0ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected ? fully static operation t he STC62WV5128 is a hig h performance, ve ry low power cmos static random access memory organized as 524,288 words by 8 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 0.45ua at 3.0v/25 o c and maximum access time of 55ns at 3.0v/85 o c . easy memory expansion is provided by an active low chip enable (ce) , and active low output enable (oe) and three-state output drivers. t he STC62WV5128 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. the STC62WV5128 is available in the jedec standard 32l sop , tsop , pdip, tsop ii and stsop package. ? description ? features ? block diagram ? product family ? pin configurations stc international limited. reserves the right to modi fy document contents without notice. address input buffer row decoder memory array 2048 x 2048 column i/o write driver sense amp column decoder data buffer output address input buffer data buffer input control gnd vdd oe we ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 a13 a17 a15 a18 a16 a14 a12 a7 a6 a5 a4 8 8 8 8 16 256 2048 2048 22 a11 a9 a8 a3 a2 a1 a0 a10 STC62WV5128 stc power dissipation speed ( ns ) standby ( i ccsb1 , max ) operating ( i cc , max ) pkg type STC62WV5128tc tsop - 32 STC62WV5128 stc stsop - 32 STC62WV5128 sc sop - 32 STC62WV5128 ec tsop2 - 32 STC62WV5128 pc +0 o c to +70 o c 2.4v ~ 5.5v 55 / 70 5ua 30ua 24ma 58ma pdip - 32 STC62WV5128 ti tsop - 32 STC62WV5128 sti stsop - 32 STC62WV5128si sop - 32 STC62WV5128 ei tsop2 - 32 STC62WV5128 pi - 40 o c to +85 o c 2.4v ~ 5.5v 55 / 70 10ua 60ua 25ma 60ma pdip - 32 oe a10 ce dq7 dq6 dq5 dq4 dq3 gnd dq2 dq1 dq0 a0 a1 a2 a3 a11 a9 a8 a13 we a17 a15 vcc a18 a16 a14 a12 a7 a6 a5 a4 ? STC62WV5128tc STC62WV5128stc STC62WV5128ti STC62WV5128sti 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd vcc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ? 62wv5128sc 62wv5128si 62wv5128ec 62wv5128ei 62wv5128pc 62wv5128pi product family operating temperature vcc range 55ns :3.0~5.5v vcc = 3.0v vcc = 3.0v vcc =5.0v ? data retention supply voltage as low as 1.5v ? easy expansion with ce and oe options ? three state outputs and ttl compatible 70ns :2.7~5.5v vcc =5.0v 70ns 70ns www.datasheet.in
revision 1.1 jan. 2004 2 r0201-STC62WV5128 name function a0-a18 address input these 19 address inputs select one of the 524,288 x 8-bit words in the ram ce chip enable input ce is active low. chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. dq0-dq7 data input/output ports these 8 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions stc mode we ce oe i/o operation vcc current not selected x h x high z i ccsb , i ccsb1 output disabled h l h high z i cc read h l l d out i cc write l l x d in i cc symbol parameter conditions max. unit c in input capacitance v in =0v 6 pf c dq input/output capacitance v i/o =0v 8 pf ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma STC62WV5128 range ambient temperature vcc commercial 0 o c to +70 o c 2.4v ~ 5.5v industrial -40 o c to +85 o c 2.4v ~ 5.5v www.datasheet.in
revision 1.1 jan. 2004 3 r0201-STC62WV5128 1. typical characteristics are at t a = 25 o c. 2. fmax = 1/t rc . 3. these are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. i cc sb1_max. is 5ua/30ua at vcc=3.0v/5.0v and t a =70 o c. 5. icc_ max. is 30ma(@3.0v)/70ma(@5.0v) under 55ns operation. ? data retention characteristics ( ta = -40 to + 85 o c ) 1. vcc = 1.5v, t a = + 25 o c 2. t rc = read cycle time 3. i cc dr _ max. is 0.8ua at t a =70 o c. ? dc electrical characteristics ( ta = -40 to + 85 o c ) stc ? low v cc data retention waveform ( ce controlled ) ce data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v R R Q R R Q R R Q www.datasheet.in
revision 1.1 jan. 2004 4 r0201-STC62WV5128 ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV5128 ? ac test conditions (test load and input/output reference) input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 30pf+1ttl c l = 100pf+1ttl ? ac electrical characteristics ( ta = -40 to + 85 o c ) read cycle jedec parameter name parameter name description unit t avax t rc read cycle time 55 -- -- 70 -- -- ns t avqv t aa address access time -- -- 55 -- -- 70 ns t elqv t acs chip select access time -- -- 55 -- -- 70 ns t glqv t oe output enable to output valid -- -- 30 -- -- 35 ns t elqx t clz chip select to output low z 10 -- -- 10 -- -- ns t glqx t olz output enable to output in low z 10 -- -- 10 -- -- ns t ehqz t chz chip deselect to output in high z -- -- 30 -- -- 35 ns t ghqz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns ? switching waveforms (read cycle) read cycle1 (1,2,4) t rc t oh t aa d out address t oh cycle time : 55ns min. typ. max. (vcc = 3.0~5.5v) min. typ. max. (vcc = 2.7~5.5v) cycle time : 70ns www.datasheet.in
revision 1.1 jan. 2004 5 r0201-STC62WV5128 notes: 1. we is high in read cycle. 2. devi ce is continuously selected when ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. stc STC62WV5128 read cycle3 (1,4) read cycle2 (1,3,4) t clz t chz (5) d out ce (5) t acs t oh t rc t oe d out ce oe address t clz (5) t acs t chz (1,5) t ohz (5) t olz t aa www.datasheet.in
revision 1.1 jan. 2004 6 jedec parameter name description unit t avax t wc write cycle time 55 -- -- 70 -- -- ns t e1lwh t cw chip select to end of write 55 -- -- 70 -- -- ns t avw l t as address set up time 0 -- -- 0 -- -- ns t avwh t aw address valid to end of write 55 -- -- 70 -- -- ns t wlwh t wp write pulse width 30 -- -- 35 -- -- ns t whax t wr write recovery time (ce , we) 0 -- -- 0 -- -- ns t wloz t whz write to output in high z -- -- 25 -- -- 30 ns t dvwh t dw data to write time overlap 25 -- -- 30 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghoz t ohz output disable to output in high z -- -- 25 -- -- 30 ns t whqx t ow end ot write to output active 5 -- -- 5 -- -- ns r0201-STC62WV5128 ? ac electrical characteristics ( ta = -40 to + 85 o c ) write cycle stc STC62WV5128 parameter name cycle time : 55ns min. typ. max. (vcc = 3.0~5.5v) min. typ. max. (vcc = 2.7~5.5v) ? switching waveforms (write cycle) write cycle1 (1) t wr (3) t cw (11) (2) t wp t aw t ohz (4,10) t as t dh t dw d in d out we ce oe address (5) t wc cycle time : 70ns www.datasheet.in
revision 1.1 jan. 2004 7 r0201-STC62WV5128 stc STC62WV5128 write cycle2 (1,6) t wc t cw (11) (2) t wp t aw t whz (4,10) t as t dh t dw d in d out we ce address (5) t ow (7) (8) (8,9) notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce going low to the end of write. www.datasheet.in
revision 1.1 jan. 2004 8 stc STC62WV5128 r0201-STC62WV5128 ? ordering information ? package dimensions base metal with plating c c1 section a-a b1 b sop -32 note: stc (stc international limited.) assumes no responsibili ty for t he application or use o f a ny product or circuit described herei n. stc does n ot a uthorize its products for use as cr itical components in any application in which the failu re of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. STC62WV5128 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package s: sop e: tsop 2 st: small tsop t: tsop p: pdip www.datasheet.in
revision 1.1 jan. 2004 9 stc STC62WV5128 r0201-STC62WV5128 tsop - 32 tsop2 - 32 www.datasheet.in
revision 1.1 jan. 2004 10 stc STC62WV5128 r0201-STC62WV5128 ? package dimensions (continued) pdip - 32 stsop - 32 www.datasheet.in
|
